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INTEGRATED CIRCUITS
GTL16612 18-bit GTL/GTL+ to LVTTL/TTL bidirectional latched translator (3-State)
Product specification 1999 Sep 13
Philips Semiconductors
Philips Semiconductors
Product specification
18-bit GTL/GTL+ to LVTTL/TTL bidirectional latched translator (3-State)
GTL16612
FEATURES
* 18-bit bidirectional bus interface * Translates between GTL/GTL+ logic levels (B ports) and * 5 V I/O tolerant on the LVTTL/TTL side (A ports) * No bus current loading when LVTTL/TTL output is tied to 5 V bus * 3-State buffers * Output capability: +64 mA/-32 mA on the LVTTL/TTL side * TTL input levels on control pins * Power-up reset * Power-up 3-State * Positive edge triggered clock inputs * Latch-up protection exceeds 500 mA per JESD78 * ESD protection exceeds 2000 V HBM per JESD22-A114,
200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101 (A ports); +40 mA on the GTL side (B ports) LVTTL/TTL logic levels (A ports)
DESCRIPTION
The GTL16612 is a high-performance BiCMOS product designed for VCC operation at 3.3 V with I/O compatibility up to 5 V. This device is an 18-bit universal transceiver featuring non-inverting 3-State bus compatible outputs in both send and receive directions. Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock (CPAB and CPBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is High. When LEAB is Low, the A data is latched if CPAB is held at a High or Low logic level. If LEAB is Low, the A-bus data is stored in the latch/flip-flop on the Low-to-High transition of CPAB. When OEAB is Low, the outputs are active. When OEAB is High, the outputs are in the high-impedance state. The clocks can be controlled with the clock-enable inputs (CEBA/CEAB). Data flow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA and CPBA.
QUICK REFERENCE DATA
SYMBOL tPLH tPHL CIN CI/O ICCZ PARAMETER Propagation delay An to Bn or Bn to An Input capacitance (Control pins) I/O pin capacitance Total supply current CL = 50 pF VI = 0 V or VCC Outputs disabled; VI/O = 0 V or VCC Outputs disabled CONDITIONS Tamb = 25C TYPICAL UNIT 3.3 V 1.9 4 8 12 ns pF pF mA
ORDERING INFORMATION
PACKAGES 56-Pin Plastic TSSOP Type II TEMPERATURE RANGE -40C to +85C ORDER CODE GTL16612 DGG DWG NUMBER SOT364-1
1999 Sep 13
2
853-2166 22326
Philips Semiconductors
Product specification
18-bit GTL/GTL+ to LVTTL/TTL bidirectional latched translator (3-State)
GTL16612
PIN CONFIGURATION
OEAB LEAB A0 GND A1 A2 VCC A3 A4 A5 GND A6 A7 A8 A9 A10 A11 GND A12 A13 A14 VCC A15 A16 GND A17 OEBA LEBA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 CEAB CPAB B0 GND B1 B2 NC B3 B4 B5 GND B6 B7 B8 B9 B10 B11 GND B12 B13 B14 VREF B15 B16 GND B17 CPBA CEBA
PIN DESCRIPTION
PIN NUMBER 1, 27 29, 56 2, 28 55,30 3, 5, 6, 8, 9, 10, 12, 13, 14, 15, 16, 17, 19, 20, 21, 23, 24, 26 54, 52, 51, 49, 48, 47, 45, 44, 43, 42, 41, 40, 38, 37, 36, 34, 33, 31 4, 11, 18, 25, 32, 39, 46, 53 7, 22 35 50 SYMBOL OEAB/OEBA CEBA/CEAB LEAB/LEBA CPAB/CPBA NAME AND FUNCTION A-to-B/ B-to-A Output enable input (active Low) B-to-A/A-to-B clock enable A-to-B/B-to-A Latch enable input A-to-B/B-to-A Clock input (active rising edge)
A0-A17
Data inputs/outputs (A side)
B0-B17
Data inputs/outputs (B side)
GND VCC VREF NC
Ground (0 V) Positive supply voltage GTL reference voltage No connection
SW00485
1999 Sep 13
3
Philips Semiconductors
Product specification
18-bit GTL/GTL+ to LVTTL/TTL bidirectional latched translator (3-State)
GTL16612
LOGIC SYMBOL (Positive Logic)
OEAB 1
CEAB
56
CPAB
55
LEAB
2
LEBA
28
CPBA
30
CEBA
29
OEBA
27 CE
A0
3
1D C1 CLK CE 1D C1 CLK
54
B0
To 17 other channels
SW00254
FUNCTION TABLE
INPUTS CEAB1 X X X H H L L L L OEAB1 H L L L L L L L L LEAB1 X H H L L L L L L CPAB1 X X X X X H L A X L H X X L H X X OUTPUT B Z L H BO2 BO2 L H BO2 BO3
X = Don't care H = High voltage level L = Low voltage level = Low to High Z = High impedance "off " state 1. A-to-B data flow is shown: B-to-A flow is similar but uses OEBA, LEBA, CPBA, and CEBA. 2. Output level before the indicated steady-state input conditions were established. 3. Output level before the indicated steady-state input conditions were established, provided that CPAB was Low before LEAB went Low.
1999 Sep 13
4
Philips Semiconductors
Product specification
18-bit GTL/GTL+ to LVTTL/TTL bidirectional latched translator (3-State)
GTL16612
ABSOLUTE MAXIMUM RATINGS 1, 2
SYMBOL VCC IIK VI IOK VO PARAMETER DC supply voltage DC input diode current DC input voltage3 DC output diode current DC output voltage3 VI < 0 A port B port VO < 0; A port Output in Off or High state; A port Output in Off or High state; B port A port IO OL IOH Tstg Current into any output in the LOW state B port Current into any output in the HIGH state Storage temperature range A port 80 -64 -65 to +150 mA mA C CONDITIONS RATING -0.5 to +4.6 -50 -0.5 to +7.0 V -0.5 to +4.6 -50 -0.5 to +7.0 -0.5 to +4.6 128 mA V V mA UNIT V mA
NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150C. 3. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
3.3 V RANGE LIMITS SYMBOL VCC VTT PARAMETER DC supply voltage GTL Termination voltage GTL+ GTL VREF GTL reference voltage GTL+ B port VI Input voltage Except B port B port VIH HIGH-level HIGH level input voltage Except B port B port VIL IOH IO OL Tamb LOW-level LOW level input voltage Except A port HIGH-level output current LOW-level LOW level output current A port Operating free-air temperature range -40 64 +85 C A port B port 0 VREF+50 mV 2.0 VREF-50 mV 0.8 -32 40 mA mA V TEST CONDITIONS MIN 3.0 1.14 1.35 0.74 0.9 0 MAX 3.6 1.26 V 1.65 0.87 V 1.10 VTT 5.5 V V V UNIT
1999 Sep 13
5
Philips Semiconductors
Product specification
18-bit GTL/GTL+ to LVTTL/TTL bidirectional latched translator (3-State)
DC ELECTRICAL CHARACTERISTICS (3.3 V "0.3 V RANGE)
GTL16612
LIMITS SYMBOL PARAMETER TEST CONDITIONS Temp = -40C to +85C MIN VIK VO OH Input clamp voltage High-level High level output voltage VCC = 3.0 V; IIK = -18 mA VCC = 3.0 to 3.6 V; IOH = -100 A VCC = 3.0 V; IOH = -32 mA VCC = 3.0 V; IOL = 100 A VCC = 3.0 V; IOL = 16 mA VOL Low-level output voltage VCC = 3.0 V; IOL = 32 mA VCC = 3.0 V; IOL = 64 mA VCC = 3.0 V; IOL = 40 mA VCC = 3.6 V; VI = VCC or GND VCC = 0 or 3.6 V; VI = 5.5 V II Input leakage current VCC = 3.6 V; VI = 5.5 V VCC = 3.6 V; VI = VCC VCC = 3.6 V; VI = 0 VCC = 3.6 V; VI = VTT or GND IOFF IHOLD O IEX IPU/PD ICCH ICCL ICCZ5 ICCH ICCL ICC Additional supply current per input pin2 B-Port B Port Outputs low VCC = 3 V to 3.6 V; One input at VCC-0.6 V, Other inputs at VCC or GND 7.0 0.04 12.0 0.2 mA VCC = 3.6 V Output off current Bus Hold current A outputs current, Current into an output in the High state when VO > VCC Power up/down 3-State output current3 A-Port A Port Outputs low Disabled Outputs high VI = GND or VCC, IO = 0 10.5 6.0 9.7 18.5 11.5 17.5 mA VCC = 0 V; VI or VO = 0 to 4.5 V VCC = 3 V; VI = 0.8 V VCC = 3 V; VI = 2.0 V VO = 5.5 V; VCC = 3.0 V A port 75 -75 B port 0.1 130 -140 10 1.0 5.0 125 100 9.0 /O I/O Data pins4 ort A port B port Control pins 0.1 0.1 0.5 0.1 A port 0.3 0.4 0.4 0.1 0.5 0.55 0.5 1 10 20 10 -5 5 100 A A A A A A V A A port VCC-0.2 2.0 TYP1 -0.85 VCC 2.3 0.07 0.25 0.2 0.4 V MAX -1.2 V V UNIT
VCC 1.2 V; VO = 0.5 V to VCC; VI = GND or VCC OE = Don't care Outputs high
NOTES: 1. All typical values are at VCC = 3.3 V and Tamb = 25C. 2. This is the increase in supply current for each LVTTL input at the specified voltage level other than VCC or GND 3. This parameter is valid for any VCC between 0 V and 1.2 V with a transition time of up to 10 msec. From VCC = 1.2 V to VCC = 3.3 V 0.3 V a transition time of 100 sec is permitted. This parameter is valid for Tamb = 25C only. 4. Unused pins at VCC or GND. 5. ICCZ is measured with outputs pulled up to VCC or pulled down to ground.
1999 Sep 13
6
Philips Semiconductors
Product specification
18-bit GTL/GTL+ to LVTTL/TTL bidirectional latched translator (3-State)
GTL16612
AC CHARACTERISTICS (A PORT)
GND = 0 V; tr = tf = 2.5 ns; CL = 50 pF; RL = 500 ; Tamb = -40C to +85C. GTL GTL16612 An Port VCC = 3.3 V 0.3 V VREF = 0.8 V SYMBOL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPHZ tPZL tPLZ PARAMETER Bn to An Bn to An LEBA to An LEBA to An CPBA to An CPBA to An OEBA to An OEBA to An OEBA to An OEBA to An WAVEFORM 2 2 3 3 1 1 5 5 6 6 MIN 1.6 3.0 1.6 1.6 1.9 1.8 1.5 1.4 1.3 1.2 TYP1 3.0 4.9 2.7 2.8 3.4 3.8 2.6 2.9 2.4 2.2 MAX 5.0 6.3 4.2 4.3 4.7 5.2 4.2 4.8 3.8 3.5 MIN 1.6 3.0 1.6 1.6 1.9 1.8 1.5 1.4 1.3 1.2 GTL+ VCC = 3.3 V 0.3 V VREF = 1.0 V TYP1 3.0 4.9 2.7 2.8 3.4 3.8 2.6 2.9 2.4 2.2 MAX 5.0 6.3 4.2 4.3 4.7 5.2 4.2 4.8 3.8 3.5 ns ns ns ns ns ns ns ns ns ns UNIT
NOTE: 1. Typical values are at VCC = 3.3 V, Tamb = +25C.
AC CHARACTERISTICS (B PORT)
GND = 0 V; tr = tf = 2.5 ns; CL = 30 pF; RL = 25 ; Tamb = -40C to +85C. GTL GTL16612 Bn Port VCC = 3.3 V 0.3 V VREF = 0.8 V SYMBOL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL PARAMETER An to Bn An to Bn LEAB to Bn LEAB to Bn CPAB to Bn CPAB to Bn OEAB to Bn OEAB to Bn WAVEFORM 2 2 3 3 1 1 7 7 MIN 1.4 1.3 1.7 2.1 1.8 2.3 1.1 1.6 TYP1 2.4 2.5 3.0 3.5 3.1 3.6 2.1 2.8 MAX 3.7 4.0 4.4 5.4 4.5 5.4 3.3 4.4 MIN 1.3 1.4 1.8 2.3 1.9 2.4 1.4 1.0 GTL+ VCC = 3.3 V 0.3 V VREF = 1.0 V TYP1 2.4 2.6 3.0 3.6 3.1 3.8 2.0 2.9 MAX 3.7 4.2 4.6 5.5 4.8 5.8 3.5 4.5 ns ns ns ns ns ns ns ns UNIT
NOTE: 1. Typical values are at VCC = 3.3 V, Tamb = +25C.
1999 Sep 13
7
Philips Semiconductors
Product specification
18-bit GTL/GTL+ to LVTTL/TTL bidirectional latched translator (3-State)
AC SETUP REQUIREMENTS (3.3 V 0.3 V RANGE)
GTL16612
A Port: GND = 0 V; Input tr = tf = 2.5 ns; CL = 50 pF; RL = 500 ; Tamb = -40C to +85C; VREF = 0.8 V or 1.0 V. B Port: GND = 0 V; Input tr = tf = 2.5 ns; CL = 30 pF; RL = 25 ; VREF = 0.8 V or 1.0 V. LIMITS SYMBOL PARAMETER WAVEFORM VCC = 3.3 V 0.3 V MIN ts(H) ts(L) ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) tw(H) tw(L) tw(H) Setup time, High or Low ,g Bn to CPBA Setup time, High or Low ,g An to CPAB Hold time, High or Low ,g Bn to CPBA, or An to CPAB Setup time, High or Low ,g Bn to LEBA, or An to LEAB Hold time, High or Low ,g Bn to LEBA, or An to LEAB Setup time, High or Low ,g CEAB to CPAB, or CEBA to CPBA Hold time, High or Low ,g CEAB to CPAB, or CEBA to CPBA Pulse width, High or Low ,g CPBA or CPAB Pulse width, High LEBA or LEAB 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 3 1.5 1.5 2.0 3.0 1.0 1.0 1.0 1.0 1.5 1.5 1.0 1.0 1.5 1.0 2.0 2.0 1.5 MAX ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns UNIT
1999 Sep 13
8
Philips Semiconductors
Product specification
18-bit GTL/GTL+ to LVTTL/TTL bidirectional latched translator (3-State)
GTL16612
AC WAVEFORMS
VM = 1.5 V at VCC w 3.0 V. VM = 1.5 V for A ports and control pins; VM = 0.8 V for B ports in GTL mode; VM = 1.0 V for B ports in GTL+ mode. VX = VOL + 0.3 V at VCC w 3.0 V. VY = VOH - 0.3 V at VCC w 3.0 V.
1/fMAX 3.0 V or VCC, whichever is less OEBA VM VM 3.0 V or VCC, whichever is less
CPBA or CPAB
VM
VM
0V tW(L) tPHL An or Bn VM tW(H) tPLH VM VOL VOH An or Bn
tPZH
tPHZ VOH VM VY
SW00181
SW00223
Waveform 1. Propagation delay, clock input to output, clock pulse width, and maximum clock frequency
3.0V or VCC, whichever is less 0V tPLH tPHL VOH
Waveform 5. 3-State output enable time to high level and output disable time from high level
OEBA VM VM 3.0 V or VCC, whichever is less
An or Bn
VM
VM
tPZL
tPLZ
An or Bn An or Bn VM VM VOL
VM
VX VOL
SW00176
SW00224
Waveform 2. Propagation delay, transparent mode
Waveform 6. 3-State output enable time to low level and output disable time from low level
OEAB VM VM 3.0 V or VCC, whichever is less
LEAB or LEBA
VM
VM
VM
3.0V or VCC, whichever is less
0V tW(H) tPHL VOH An or Bn VM VM VOL Bn VM VM VOL tPLH tPLH tPHL
SW00177
SW00495
Waveform 3.
Propagation delay, enable to output, and enable pulse width
Waveform 7.
Output enable time on open collector output with pullup
An or Bn CEAB or CEBA VM VM
VM
VM
3.0 V or VCC, whichever is less 0V
CPAB or CPBA, LEAB or LEBA
1999 Sep 13
EEE EEEE EEE EEE EEEE EEE
tS(H) th(H) tS(L) th(L) VM VM
3.0 V or VCC, whichever is less 0V SW00222
Waveform 4. Data setup and hold times
9
Philips Semiconductors
Product specification
18-bit GTL/GTL+ to LVTTL/TTL bidirectional latched translator (3-State)
GTL16612
TEST CIRCUIT
VCC 6.0 V or VCC x 2
Open
VIN D.U.T. RT CL RL = 500 VOUT RL = 500
90% NEGATIVE PULSE VM 10% tTHL (tF) tTLH (tR) 90%
tW VM 10%
90%
VIN
GND
PULSE GENERATOR
0V tTLH (tR) tTHL (tF) VIN VM 10% tW 0V
90%
Test Circuit for A Outputs
1.2 V 25 FROM OUTPUT UNDER TEST CL = 30 pF (INCLUDES PROBE AND JIG CAPACITANCE) TEST POINT
POSITIVE PULSE 10%
VM
Load Circuit for B Outputs
SWITCH POSITION
TEST tPLZ/tPZL tPLH/tPHL tPHZ/tPZH SWITCH 6V Open GND
DEFINITIONS
RL = Load resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance: See AC CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators. 74GTL16 FAMILY Amplitude
INPUT PULSE REQUIREMENTS Rep. Rate tW tR tF
3.0 V or VCC whichever is less
v10 MHz 500 ns v2.5 ns v2.5 ns
SW00255
1999 Sep 13
10
Philips Semiconductors
Product specification
18-bit GTL/GTL+ to LVTTL/TTL bidirectional latched translator (3-State)
GTL16612
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1mm
SOT364-1
1999 Sep 13
11
Philips Semiconductors
Product specification
18-bit GTL/GTL+ to LVTTL/TTL bidirectional latched translator (3-State)
GTL16612
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1999 All rights reserved. Printed in U.S.A. Date of release: 09-99 Document order number: 9397-750-06414
Philips Semiconductors
1999 Sep 13 12

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